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34 com / 80 seg driver & controller for stn lcd nov.1999 . ver. 0.4 prepared by : won- sik, kang k2w3@samsung.co.kr KS0094 contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.

34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 1 ks009 4 specification revision history version content date 0.0 original apr. 1999 0.1 cgrom font table added at table 5 com data shift direction changed at table 9 read data instruction separation according to re bit at table 10 symbol register is changed to iconram at table 12 idd1 is changed at table 18, 19 may.1999 0.2 idd1 is changed at table 18, 19 jun.1999 0.3 pad location added at table 1 and 2 july.1999 0.4 vdd change (2.4v~5.5v -> 2.4v~3.6v) nov. 199 9
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 2 contents introduction ................................ ................................ ................................ ................................ .......... 1 features ................................ ................................ ................................ ................................ ................. 1 block diagram ................................ ................................ ................................ ................................ ...... 3 pad configuration ................................ ................................ ................................ .............................. 4 pad center coordinates ................................ ................................ ................................ .................. 5 pin description ................................ ................................ ................................ ................................ ...... 6 power supply ................................ ................................ ................................ ................................ . 6 lcd driver supply ................................ ................................ ................................ ......................... 6 system control ................................ ................................ ................................ ............................. 7 mpu interface ................................ ................................ ................................ ................................ 8 lcd driver outputs ................................ ................................ ................................ ...................... 8 test ................................ ................................ ................................ ................................ .................... 8 function description ................................ ................................ ................................ .......................... 9 system interface ................................ ................................ ................................ .......................... 9 address counter (ac) ................................ ................................ ................................ ................ 13 display data ram (ddram) ................................ ................................ ................................ ......... 13 character generator rom (cgrom) ................................ ................................ ..................... 13 character generator ram (cgram) ................................ ................................ ..................... 19 segment icon ram (iconram) ................................ ................................ ................................ .... 20 high power mode ................................ ................................ ................................ ......................... 22 low power consumption mode ................................ ................................ .............................. 22 lcd driver circuit ................................ ................................ ................................ ....................... 23 instruction description ................................ ................................ ................................ .................. 24 initializing & power save mode setup ................................ ................................ ......................... 35 hardware reset ................................ ................................ ................................ .......................... 35 initializing and power save setup ................................ ................................ ......................... 37 lcd driving power supply circuit ................................ ................................ ................................ 40 voltage converter ................................ ................................ ................................ .................... 40 voltage regulator ................................ ................................ ................................ .................... 41 electronic contrast control (32 steps) ................................ ................................ ........... 42 voltage generator circuit ................................ ................................ ................................ .... 44 mpu interface ................................ ................................ ................................ ................................ ...... 45 application information for lcd panel ................................ ................................ .................... 47 frame frequency ................................ ................................ ................................ ............................... 51 maximum absolute ratings ................................ ................................ ................................ ............. 52 electrical characteristics ................................ ................................ ................................ .......... 53 dc characteristics ................................ ................................ ................................ .................... 53 ac characteristics ................................ ................................ ................................ .................... 54
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 1 introduction the KS0094 is an lcd driver and controller lsi for liquid crystal dot matrix character display systems. it can display 2, 3 or 4 lines of 16 characters with 5 x 8 dots format. it is capable of interfacing various microprocessors, supporting the 4-bit, 8-bit parallel modes and the clock synchronized serial mode. voltage converter, oscillator, voltage regulator, voltage follower and bias circuit are built in the ic. the double height character mode and line vertical scroll functions are supported. features driver outputs - common outputs: 34 common - segment outputs: 80 segment applicable panel size font display duty contents of outputs 2 -line x 16 characters 1 / 18 2 x 16 characters + 16 0 icons 3 -line x 16 characters 1 / 26 3 x 16 characters + 16 0 icons 5 x 8 4 -line x 16 characters 1 / 34 4 x 16 characters + 16 0 icons internal memory - character generator rom (cgrom): 21 , 760 bits ( 544 characters x 5 x 8 dots) - character generator ram (cgram): 240 bits ( 6 characters x 5 x 8 dots) - display data ram (ddram): 640 bits (16 characters x 5 lines ) - segment icon ram (iconram): 16 0 bits ( 160 icons) mpu interface - no busy mpu interface (no busy check or no execution waiting time) - 8 -b it p arallel i nterface m ode: 68-series and 80-series are available - 4 -b it p arallel i nterface m ode: 68-series and 80-series are available - serial i nterface m ode: 4 - pin clock synchronized serial interface function set - various instructions set: display control, power save, power control, etc. - com / seg bi-directional ( 4-type lcd application available) - h/w reset (resetb) built-in analog circuit - internal rc oscillator circuit or external clock - electronic volume for contrast control (32 steps) - voltage converter / voltage regulator / voltage follower & bias circuit low power operation - sleep mode operation (5ua max.) - normal mode operation ( tbd)
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 2 operating voltage range - power supply voltage (v dd ): 2.2v ? 3.6v - lcd driving voltage (vlcd = v0 - v ss ): 7 .0v max. package type - gold bumped c hip
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 3 block diagram parallel interface 4 bit/8 bit serial interface input buffer instruction register (ir) 8 instruction decoder address counter display data ram (ddram) 640 bits data register (dr) 8 icon ram 160 bits character generator ram (cgram) 240 bits character generator rom (cgrom) 21760 bits cursor and blink controller common driver 34 bits shift register segment driver 80 bits latch circuit 80 bits shift register lcd driver voltage selector segment data conversion lcd driving power circuit voltage converter voltage regulator voltage follower & bias resistor timing generator oscillator seg1- seg80 m i csb rs rw_wr e_rd db7 (si) db6 (scl) db5- db4 db3- db0 resetb ps if cap1+ cap1- cap2+ cap2- vout v0 vr v1 v2 v3 v4 dirs ck com1- com 32 com i1 com i2 v dd gnd 7 8 8 8 5 5 8 8 data output register (or) 8 duty1 duty0 figure 1. block diagram
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 4 pad configuration (not fixed) ............................ ........................... ... .. ... x y (0,0) dummy pad pad 1 61 62 8 1 82 1 64 1 83 163 figure 2. pad configuration table 1. KS0094 pad dimensions size item pad no. x y unit chip size - 6320 1860 1 ? 66 90 63~80,83~162 , 165~182 70 pad pitch 62,81,82,163,164,183 90 m m 1~61 60 100 63~80 100 50 83~162 50 100 165~182 100 50 62,81 100 60 82,163 60 100 bumped pad size 164,183 100 60 bumped pad height all pad 1 7 ( typ.) cog align key coordinate ilb align key coordinate 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m 42 m m 108 m m 30 m m 30 m m 30 m m (+2830 , - 830) 30 m m 30 m m 30 m m 30 m m 30 m m 30 m m ( - 2830, - 835) 60 m m 30 m m (-3 110 , +880) (+3110, +880)
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 5 pad center coordinates table 2. p ad center coordinates [unit: m m ] pad pad pad pad pad pad no name no name no name 1 rs -2700 -820 62 dummy1 3050 -700 123 seg41 -35 820 2 vss -2610 -820 63 comi1 3050 -620 124 seg42 -105 820 3 rw_wr -2520 -820 64 com1 3050 -550 125 seg43 -175 820 4 vdd -2430 -820 65 com2 3050 -480 126 seg44 -245 820 5 e_rd -2340 -820 66 com3 3050 -410 127 seg45 -315 820 6 vss -2250 -820 67 com4 3050 -340 128 seg46 -385 820 7 csb -2160 -820 68 com5 3050 -270 129 seg47 -455 820 8 db7 -2070 -820 69 com6 3050 -200 130 seg48 -525 820 9 db6 -1980 -820 70 com7 3050 -130 131 seg49 -595 820 10 db5 -1890 -820 71 com8 3050 -60 132 seg50 -665 820 11 db4 -1800 -820 72 com9 3050 10 133 seg51 -735 820 12 db3 -1710 -820 73 com10 3050 80 134 seg52 -805 820 13 db2 -1620 -820 74 com11 3050 150 135 seg53 -875 820 14 db1 -1530 -820 75 com12 3050 220 136 seg54 -945 820 15 db0 -1440 -820 76 com13 3050 290 137 seg55 -1015 820 16 vdd -1350 -820 77 com14 3050 360 138 seg56 -1085 820 17 vdd -1260 -820 78 com15 3050 430 139 seg57 -1155 820 18 vss -1170 -820 79 com16 3050 500 140 seg58 -1225 820 19 vss -1080 -820 80 comi1 3050 570 141 seg59 -1295 820 20 v4 -990 -820 81 dummy2 3050 650 142 seg60 -1365 820 21 v4 -900 -820 82 dummy3 2845 820 143 seg61 -1435 820 22 v3 -810 -820 83 seg1 2765 820 144 seg62 -1505 820 23 v3 -720 -820 84 seg2 2695 820 145 seg63 -1575 820 24 v2 -630 -820 85 seg3 2625 820 146 seg64 -1645 820 25 v2 -540 -820 86 seg4 2555 820 147 seg65 -1715 820 26 v1 -450 -820 87 seg5 2485 820 148 seg66 -1785 820 27 v1 -360 -820 88 seg6 2415 820 149 seg67 -1855 820 28 v0 -270 -820 89 seg7 2345 820 150 seg68 -1925 820 29 v0 -180 -820 90 seg8 2275 820 151 seg69 -1995 820 30 v0 -90 -820 91 seg9 2205 820 152 seg70 -2065 820 31 v0 0 -820 92 seg10 2135 820 153 seg71 -2135 820 32 vr 90 -820 93 seg11 2065 820 154 seg72 -2205 820 33 vr 180 -820 94 seg12 1995 820 155 seg73 -2275 820 34 vss 270 -820 95 seg13 1925 820 156 seg74 -2345 820 35 duty1 360 -820 96 seg14 1855 820 157 seg75 -2415 820 36 vdd 450 -820 97 seg15 1785 820 158 seg76 -2485 820 37 duty0 540 -820 98 seg16 1715 820 159 seg77 -2555 820 38 vss 630 -820 99 seg17 1645 820 160 seg78 -2625 820 39 vout 720 -820 100 seg18 1575 820 161 seg79 -2695 820 40 vout 810 -820 101 seg19 1505 820 162 seg80 -2765 820 41 cap2- 900 -820 102 seg20 1435 820 163 dummy4 -2845 820 42 cap2- 990 -820 103 seg21 1365 820 164 dummy5 -3050 650 43 cap2+ 1080 -820 104 seg22 1295 820 165 comi2 -3050 570 44 cap2+ 1170 -820 105 seg23 1225 820 166 com32 -3050 500 45 cap1- 1260 -820 106 seg24 1155 820 167 com31 -3050 430 46 cap1- 1350 -820 107 seg25 1085 820 168 com30 -3050 360 47 cap1+ 1440 -820 108 seg26 1015 820 169 com29 -3050 290 48 cap1+ 1530 -820 109 seg27 945 820 170 com28 -3050 220 49 vss 1620 -820 110 seg28 875 820 171 com27 -3050 150 50 dirs 1710 -820 111 seg29 805 820 172 com26 -3050 80 51 vdd 1800 -820 112 seg30 735 820 173 com25 -3050 10 52 ck 1890 -820 113 seg31 665 820 174 com24 -3050 -60 53 vss 1980 -820 114 seg32 595 820 175 com23 -3050 -130 54 ps 2070 -820 115 seg33 525 820 176 com22 -3050 -200 55 vdd 2160 -820 116 seg34 455 820 177 com21 -3050 -270 56 if 2250 -820 117 seg35 385 820 178 com20 -3050 -340 57 vss 2340 -820 118 seg36 315 820 179 com19 -3050 -410 58 mi 2430 -820 119 seg37 245 820 180 com18 -3050 -480 59 vdd 2520 -820 120 seg38 175 820 181 com17 -3050 -550 60 resetb 2610 -820 121 seg39 105 820 182 comi2 -3050 -620 61 test 2700 -820 122 seg40 35 820 183 dummy6 -3050 -700 x y x y x y
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 6 pin description power s upply table 3. pin description name i/o description vdd power supply connect to mpu power supply pin vss power 0v (gnd) bias voltage level for lcd driving voltages should have the following relationship; v0 3 v1 3 v2 3 v3 3 v4 3 v ss when the built-in power circuit is active and internal 1/5 bias resist o rs are used. lcd bias v1 v2 v3 v4 1/5 bias (4/5) x v0 (3/5) x v0 (2/5) x v0 (1/5) x v0 when the built-in power circuit is active and internal 1/4 bias resist o rs are used. lcd bias v1 v2 v3 v4 1/4 bias (3/4) x v0 (2/4) x v0 (1/4) x v0 v0 v1 v2 v3 v4 i/o lcd d river s upply table 3. pin description (continued) name i/o description cap1+ o capacitor + connecting pin for the internal voltage converter cap1- o capacitor - connecting pin for the internal voltage converter cap2+ o capacitor + connecting pin for the internal voltage converter cap2- o capacitor - connecting pin for the internal voltage converter vout i/o dc/dc voltage converter output vr i voltage adjust pin this pin gives a voltage between v0 and v ss by resistance-division of voltage.
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 7 system c ontrol table 3. pin description (continued) name i/o description ck i external clock input it must be fixed to "high" or "low" when the internal oscillation circuit is used. in case of the external clock mode, ck is used as the clock and os bit should be off. mi i mpu interface selection input mi = "low": 80 series mpu mi = "high": 68 series mpu ps i parallel / serial selection input when ps = "low": serial mode when ps = "high": 4-bit/8-bit bus mode if i interface data length selection pin for parallel data input when ps = "low" if = "low" or "high": serial interface mode when ps = ?high? if = "low": 4-bit bus mode if = "high": 8-bit bus mode dirs i seg direction selection input when dirs = "low? seg1 ? seg2 ? seg79 ? seg80 when dirs = "high? seg80 ? seg79 ? seg2 ? seg1 display l ine m ode selection input d uty 1 d uty 0 mode d uty 0 0 2-line 1/18 0 1 3-line 1/26 1 0/1 4-line 1/34 duty1 duty0 i
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 8 mpu i nterface table 3. pin description (continued) name i/o description resetb i reset input ks009 4 is initialized while resetb is low. csb i chip selection input ks009 4 is selected while csb is low. rs i register selection input when rs = "low", instruction register when rs = "high", data register rw_wr i in 80-series mpu interface mode this pin is connected to wr pin of mpu and is a n active low write signal. in 68-series mpu interface mode this pin is connected to r/w pin of mpu . when rw_wr = "low", write mode when rw_wr = "high", read mode e_rd i in 80-series mpu interface mode this pin is connected to rd pin of mpu and is a active low read signal . in 68-series mpu interface mode this pin is connected to e pin of mpu and enable read or write command according to rw_wr signal . db0 - db3 db4 - db5 db6 (scl), db7 (si) i/o when 8-bit bus mode, used as bi-directional data bus db0 - db7 . during 4-bit bus mode, only db4 - db7 are used. in this case db0 - db3 pins are not used. when serial mode, db6 (scl) is used as serial clock input pin and db7 (si) is used as serial data input pin. lcd d river o utputs name i/o description com1 ? com32 o common signal output for driving lcd comi1, comi2 o common signal output for icon display seg1 ? seg80 o segment signal output for driving lcd t est name i/o description test i test pin this pin is not used for normal operation. open at normal operation mode note: dummy ? these pins should be opened (floated).
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 9 function description system interface KS0094 has two kinds of interface type with mpu: bus mode, serial mode. serial or bus mode is selected by ps pin. in bus mode, 4-bit bus or 8-bit bus is selected by if pin, and 68 series mpu or 80 series mpu is selected by mi pin. table 4. various kinds of mpu interface according to ps, mi and if ps mi if csb rs rw_wr e_rd db0 ~ ~ db3 db4 ~ ~ db5 db6 db7 8 bit (h) csb rs r/w e db0 ~ db3 db4 ~ db5 db6 db7 68 series (h) 4 bit (l) csb rs r/w e * (1) db4 ~ db5 db6 db7 8 bit (h) csb rs wr rd db0 ~ db3 db4 ~ db5 db6 db7 bus mode (h) 80 series (l) 4 bit (l) csb rs wr rd * db4 ~ db5 db6 db7 serial mode (l) (h)/(l) (2) (h)/(l) csb rs (h)/(l) (h)/(l) * * scl si notes: 1. ? * ? : don?t care (high, low or open) 2. ? (h)/(l) ? : fixed high (v dd ) or low (v ss ) ps: "high" = bus mode, "low" = serial mode mi: "high" = 68-series mpu, "low" = 80-series mpu if: "high" = 8-bit mode, "low" = 4-bit mode (ps: "high") csb: "high" = chip is not selected, "low" = chip is selected rs: "high" = data register, "low" = instruction register rw_wr : r ead / w rite indicating signal in 68 mode or active low signal for enabling write in 80 mode. e_rd: active high signal for enabling command is 68 mode or active low signal for enabling read in 80 mode. scl (db6): serial clock input si (db7): serial data input
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 10 interface with mpu in parallel mode (ps = "high") during writing operation, two 8-bit registers, data register (dr) and instruction register (ir), are used. the data register (dr) is used as temporary data storage place for being written into ddram / cgram / iconram and one of these ram is selected by ram address setting instruction. the instruction register (ir) is used only to store instruction code transferred from mpu. to select dr or ir register, rs input pin is used. during reading operation, 8-bit register, output data register (or) is used. the output data register (or) is used as temporary data storage place for being read from ddram / cgram / iconram and one of these ram is selected by ram address setting instruction. after ram address setting, first reading is a dummy cycle in 8-bit bus mode ( f igure 3, 4). the valid data comes from second reading. in 4-bit bus mode, after ram address setting, first and second reading are dummy cycles ( f igure 5, 6). the valid data comes from third reading. the dummy read make the address counter (ac) increased by 1. so it is recommended to set address again before writing. the instruction read cycle is not supported and it is regarded as a no operation cycle. in 4-bit bus mode, it is needed to transfer 4-bit data (through db7-db4) by two times. the high order bits (for 8-bit mode db7-db4) are written before the low order bits (for 8-bit mode db3-db0) in write and low order bits (for 8-bit mode db3-db0) are read before the high order bits (for 8-bit mode db7-db4) in read transaction. the db0-db3 pins are floated in this 4-bit bus mode. after resetb resets, KS0094 considers first 4-bit data from mpu as the high order bits. mi csb rs rw_wr e_rd db7-db0 instruction write dummy read data write nop ram read valid data if figure 3. timing diagram of 8-bit parallel bus mode data transfer (68-series mpu mode)
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 11 mi csb rs rw_wr e_rd db7-db0 instruction write dummy read data write nop ram read valid data if figure 4. timing diagram of 8-bit parallel bus mode data transfer (80-series mpu mode) mi csb rs rw_wr e_rd db7-db4 instruction write dummy read data write nop ram read lower 4-bit upper 4-bit upper 4-bit lower 4-bit lower 4-bit upper 4-bit if figure 5. timing diagram of 4-bit parallel bus mode data transfer (68-series mpu mode) mi csb rs rw_wr e_rd db7-db4 instruction write dummy read data write nop ram read lower 4-bit upper 4-bit upper 4-bit lower 4-bit lower 4-bit upper 4-bit if figure 6. timing diagram of 4-bit parallel bus mode data transfer (80-series mpu mode)
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 12 interface with mpu in serial mode (ps = "low") when ps input pin is "low", clock synchronized serial interface mode is selected. at this time, four ports, scl (db6, synchronizing transfer clock), si (db7, serial input data), rs (register selection input) and csb (chip selection input) are used. by setting csb to "low", KS0094 can receive scl input. if csb is set to "high", KS0094 resets the internal 8-bit shift register and 3-bit counter. serial data is input in the order of "d7, d6, d5, d4, d3, d2, d1, d0" from the serial data input pin (si = db7) at the rising edge of serial clock (scl = db6). at the rising edge of the 8th serial clock, the serial data (d7-d0) is converted into 8 bit bus mode data. the rs input of the dr/ir selection is latched at the rising edge of the 8th serial clock (scl). in serial mode, the read is not possible. rs scl (db6) si (db7) csb d7 d6 d5 d4 d3 d2 d1 d0 d7 1 2 3 4 5 6 7 8 9 figure 7. timing diagram of serial data transfer
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 13 address counter (ac) address counter (ac) in KS0094 stores ddram / cgram / iconram address. after writing into or reading from ddram / cgram / iconram, ac is automatically increased by 1. the address counter is only one and stores the address among ddram / cgram / iconram. display data ram (ddram) ddram stores display data of maximum 80 x 8 bits (max. 80 characters). ddram address is set in the address counter (ac) as a hexadecimal number. 3 4 3 5 3 6 3 7 3 8 3 9 3 a 3 b 3 c 3 d 3 e 3 f 3 0 3 1 3 2 3 3 4 4 4 5 4 6 4 7 4 8 4 9 4 a 4 b 4 c 4 d 4 e 4 f 4 0 4 1 4 2 4 3 5 4 5 5 5 6 5 7 5 8 5 9 5 a 5 b 5 c 5 d 5 e 5 f 5 0 5 1 5 2 5 3 com1 ~ com8 com9 ~ com16 com17 ~ com24 seg1 seg80 1st ch . 16th ch . ddram address in 4 line display 6 4 6 5 6 6 6 7 6 8 6 9 6 a 6 b 6 c 6 d 6 e 6 f 6 0 6 1 6 2 6 3 com25 ~ com32 7 4 7 5 7 6 7 7 7 8 7 9 7 a 7 b 7 c 7 d 7 e 7 f 7 0 7 1 7 2 7 3 hidden line figure 8. ddram address character generator rom (cgrom) cgrom has one main rom and four option rom . the main cgrom has 160 characters and the option cgroms ha ve 96 characters each. the total cgrom has 5 x 8-dot 544 characters . the r1, r0 bits select an option cgrom between 4 option cgrom. if one of 4 cgrom is selected, the other cgrom font can not be used. the cg bit of the instruction table selects the 6 characters (00h ~ 05h) of cgrom or cgram.
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 14 table 5 . cgrom character code ( main rom )
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 15 table 5 . cgrom character code ( o ption rom 1) (continued)
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 16 table 5 . cgrom character code ( option rom2 ) (continued)
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 17 table 5 . cgrom character code ( option rom3 ) (continued)
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 18 table 5 . cgrom character code ( o ption rom 4 ) (continued)
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 19 character generator ram (cgram) cgram has up to 5 x 8-dot 6 characters. by writing font data to cgram, user defined character can be used . cgram can be written regardless of cg bit . table 6. relationship between character code (ddram) and character pattern (cgram) character code (ddram data) cgram address cgram data d7 d6 d5 d4 d3 d2 d1 d0 re a6 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 pattern number 0 0 0 0 0 0 0 0 (00h) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 - - - 0 1 0 1 0 - - - 1 0 1 0 1 - - - 0 1 0 1 0 - - - 1 0 1 0 1 - - - 0 1 0 1 0 - - - 1 0 1 0 1 - - - 0 1 0 1 0 - - - 1 0 1 0 1 pattern 1 0 0 0 0 0 0 0 1 (01h) 1 0 0 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 - - - 0 0 0 0 0 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 1 1 1 1 1 pattern 2 0 0 0 0 0 0 1 0 (02h) 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 0 0 0 1 0 1 1 1 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 - - - 0 1 0 1 0 pattern 3 0 0 0 0 0 0 1 1 (03h) 1 0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1 - - - 0 1 1 1 0 - - - 1 0 1 0 1 - - - 1 1 0 1 1 - - - 1 0 1 0 1 - - - 0 1 1 1 0 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 pattern 4 note : ? - ? - don?t care
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 20 table 6 . relationship between character code (ddram) and character pattern (cgram) ( continued ) character code (ddram data) cgram address cgram data d7 d6 d5 d4 d3 d2 d1 d0 re a6 a5 a4 a3 a2 a1 a0 p7 p6 p5 p4 p3 p2 p1 p0 pattern number 0 0 0 0 0 1 0 0 (04h) 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 - - - 1 1 0 1 1 - - - 1 0 0 0 1 - - - 0 0 0 0 0 - - - 1 0 0 0 1 - - - 1 1 0 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 pattern 5 0 0 0 0 0 1 0 1 (05h) 1 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 1 0 1 1 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 0 1 0 1 1 1 1 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 0 0 0 0 0 - - - 1 1 1 1 1 - - - 1 1 1 1 1 - - - 0 0 0 0 0 - - - 0 0 0 0 0 pattern 6 note : ? - ? - don?t care segment icon ram (iconram) iconram has segment control data and segment pattern data. the number of icons is 16 0. comi2 comi1 s1 s5 ?? s81 s85 ?? s76 s80 ?? s156 s160 ?? figure 9. relationship between iconram and icon display
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 21 table 7 . relationship between iconram address and display pattern iconram bits re iconram address d7 d6 d5 d4 d3 d2 d1 d0 1 60h - - - s1 s2 s3 s4 s5 1 61h - - - s6 s7 s8 s9 s10 1 62h - - - s11 s12 s13 s14 s15 . . . . 1 6dh - - - s66 s67 s68 s69 s70 1 6eh - - - s71 s72 s73 s74 s75 1 6fh - - - s76 s77 s78 s79 s80 1 7 0h - - - s 8 1 s 8 2 s 8 3 s 8 4 s 8 5 1 7 1h - - - s 8 6 s 8 7 s 8 8 s 8 9 s 9 0 1 7 2h - - - s 9 1 s 9 2 s 9 3 s 9 4 s 9 5 . . . . 1 7 dh - - - s 14 6 s 14 7 s 14 8 s 14 9 s 15 0 1 7 eh - - - s 15 1 s 15 2 s 15 3 s 15 4 s 15 5 1 7 fh - - - s 15 6 s 15 7 s 15 8 s 15 9 s 16 0 note : ? - ? - don?t care . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 22 high power mode the power circuit built-in the KS0094 is a low power consumption type (when the h igh p ower mode is off). accordingly, in the case of a large load liquid crystal or panel, the display quality may be degraded. in the case, the display quality can be improved by entering hpm = ? 1 ? by command. before determining whether or not to use this mode. it is recommended to make a display check with real machine. in the case, the display quality cannot be improved satisfactorily though the power mode is set , a liquid crystal driver power must be supplied from the outside. low power consumption mode KS0094 provides with sleep mode for saving power consumption during standby period. sleep mode (power save bit on, oscillation bit off) to enter the sleep mode, the power circuit and oscillation circuit should be turned off by using the power save command and the power control command. this mode helps to save power consumption by reducing current to reset level. 1. liquid crystal display output com1 - com32, comi1, comi2 : v ss level seg1 - seg80 : v ss level 2. data written in ddram, cgram, iconram and registers are remained as previous value. 3. operation mode is retained the same as it was prior to execution of the sleep mode. all internal circuits are stopped. 4. power circuit and oscillation circuit the built-in power supply circuit and oscillation circuit are turned off by power save command and power control command.
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 23 lcd driver circuit lcd driver circuit has 34 common s and 80 segment s signals for driving lcd. data from iconram / cgram / cgrom are transferred to 80-bit segment register serially, and then they are stored to 80-bit shift latch. in case of 2-line display mode com1 - com16, comi1 and comi2 have 1/18 duty, in 3-line mode com1 - com24, comi1 and comi2 have 1/26 duty, and in 4-line mode com1 - com32, comi1 and comi2 have 1/34 duty ratio . seg bi- directional function is selected by dirs input pin, and com shift direction is selected by function set instruction "s s " bit. table 8 . seg data shift direction dir s pin seg data shift direction low seg1 ? seg2 ? seg3 ................... seg78 ? seg79 ? seg80 high seg80 ? seg79 ? seg78 ................... seg3 ? seg2 ? seg1 table 9 . com data shift direction line mode c s com data shift direction 0 (left) com1 ? com2 .. ?? .. com15 ? com16 ? comi1 ? comi2 2-line mode 1 (right) com16 ? com15 ?? . .... com2 ? com 1 ? comi 1 ? comi 2 0 (left) com1 ? com2 ............ com23 ? com24 ? comi1 ? comi2 3-line mode 1 (right) com24 ? com23 ..... ? . ..... com2 ? com1 ? comi 1 ? comi 2 0 (left) com1 ? com2 .......?. com31 ? com32 ? comi1 ? comi2 4-line mode 1 (right) com32 ? com31 .. ?? . ... com2 ? com1 ? comi 1 ? comi 2
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 24 instruction description table 10 . instruction table instruction re rs db7 db6 db5 db4 db3 db2 db1 db0 description 0 0 0 0 0 1 * * * * ddram address is set to 30h from ac and the cursor returns to home position the contents of ddram are not changed. return home l ine s hift 1 0 0 0 0 1 * * ls1 ls0 determination of the ddram line which is displayed at the first line at lcd ls 1 , ls 0 = 00: ddram line 1 shows at the first line of lcd (default) 01: ddram line 2 shows at the first line of lcd 10: ddram line 3 shows at the first line of lcd 11: ddram line 4 shows at the first line of lcd 0 0 0 0 1 0 lb4 lb3 lb2 lb1 line blink mode lb4 = 0: ddram4 is normal display (default) 1: ddram4 is blink mode lb3 = 0: ddram3 is normal display (default) 1: ddram3 is blink mode lb2 = 0: ddram2 is normal display (default) 1: ddram2 is blink mode lb1 = 0: ddram1 is normal display (default) 1: ddram1 is blink mode line b link double height 1 0 0 0 1 0 dh4 dh3 dh2 dh1 doubled height mode dh4 = 0: ddram4 is normal display (default) 1: ddram4 is double height dh3 = 0: ddram3 is normal display (default) 1: ddram3 is double height dh2 = 0: ddram2 is normal display (default) 1: ddram2 is double height dh1 = 0: ddram1 is normal display (default) 1: ddram1 is double height display control 0/1 0 0 0 1 1 c b re d cursor / blink / display on / off c = 0: cursor off (default) 1: cursor on b = 0: blink off (default) 1: blink on re=0: extension register off (default) 1: extension register on d = 0: display off (default) 1: display on power save 0/1 0 0 1 0 0 * * os ps power save / oscillation circuit on / off os = 0: oscillator off (default) 1: oscillator on ps = 0: power save off (default) 1: power save on
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 25 table 10 . instruction table (continued) instruction re rs db7 db6 db5 db4 db3 db2 db1 db0 description 0 0 0 1 0 1 hpm vr vf vc lcd power control hpm = 0: h igh power mode off (default) 1: high power mode on vr = 0 : voltage regulator off (default) 1 : voltage regulator on vf = 0 : voltage follower off (default) 1 : voltage follower on vc = 0 : voltage converter off (default) 1 : voltage converter on power control 1 0 0 1 0 1 irs bs ir1 ir0 internal resistor select irs = 0: external resistors are used for regulator (default) 1: internal resistors are used for regulator lcd bias select bs = 0: 1/5 bias (default) 1: 1/4 bias internal resistor ratio select ir1, ir0 = 00: (1+rb/ra) = 2.81 01: (1+rb/ra) = 3.27 10: (1+rb/ra) = 3.50 11: (1+rb/ra) = 3.00 0 0 0 1 1 0 r1 r0 c s cg option cgrom select r 1,r0 = 00: m ain rom + o ption rom1 (default) 01: m ain rom + o ption rom2 10: m ain rom + o ption rom3 11: m ain rom + o ption rom4 shifting direction of com cs = 0: com1 ? com32 (default) 1: com32 ? com1 select cgram or cgrom cg = 0: cgrom (default) , 1: cgram system set 1 0 0 1 1 0 * * ss * segment symmetry of each segment character ss = 0: normal character display (default) 1: symmetrical character display 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 ddram or electronic volume address range: 30 h - 7fh dd ram / cgram address set 1 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 cgram or segment icon ram address range: 00 h - 2fh write data 0/1 1 d7 d6 d5 d4 d3 d2 d1 d0 write ddram / cgram / iconram /electronic volume ram this is determined by the address set instruction executed immediately before writing data. read data 0/1 1 d7 d6 d5 d4 d3 d2 d1 d0 read ddram / cgram / iconram this is determined by the address set instruction executed immediately before reading data. nop 0/1 0 0 0 0 0 0 0 0 0 non-operation instruction test 0/1 0 0 0 0 0 * * * * don?t use this instruction notes: 1. "-": don?t care 2. "*": don?t use
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 26 return home re rs db7 db6 db5 db4 db3 db2 db1 db0 0 1 0 0 0 1 * * * * *: d on ? t care return home instruction field makes cursor return home. ddram address is set to 30 h from address counter and the cursor returns to home position. the contents of ddram are not changed. line shift mode re rs db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 0 1 * * ls2 ls1 *: d on ? t care line shift m ode instruction field selects the ddram to be displayed in first line. ls 1 , ls 0 = 00: s croll amount 0 line (default) 01: s croll 1 line upward (display line 1 from ddram line 2) 10: s croll 2 line upward (display line 2 from ddram line 3) 11: s croll 2 line upward (display line 3 from ddram line 4) dd ram line2 ( 4 0h~ 4 fh) dd ram line3 ( 5 0h~ 5 fh) dd ram line4 ( 6 0h~ 6 fh) dd ram line 5 ( 7 0h~ 7 fh) lcd ls2, ls1 = 01 dd ram line3 ( 5 0h~ 5 fh) dd ram line4 ( 6 0h~ 6 fh) dd ram line 5 ( 7 0h~ 7 fh) dd ram line 1 ( 3 0h~ 3 fh) lcd ls2, ls1 = 10 dd ram line4 ( 6 0h~ 6 fh) dd ram line5 ( 7 0h~ 7 fh) dd ram line 1 ( 3 0h~ 3 fh) dd ram line2 ( 4 0h~ 4 fh) lcd ls2, ls1 = 11 dd ram line1 ( 3 0h~ 3 fh) dd ram line2 ( 4 0h~ 4 fh) dd ram line3 ( 5 0h~ 5 fh) dd ram line1 ( 3 0h~ 3 fh) dd ram line2 ( 4 0h~ 4 fh) dd ram line3 ( 5 0h~ 5 fh) dd ram line4 ( 6 0h~ 6 fh) lcd ls2, ls1 = 00 dd ram line 5 ( 7 0h~ 7 fh) figure 1 0 . line shift mode display at 3-line lcd ls2, ls1 = 01 dd ram line 2 ( 4 0h~ 4 fh) ls2, ls1 = 10 dd ram line 3 ( 5 0h~ 5 fh) ls2, ls1 = 11 dd ram line1 (30h~ 3 fh) dd ram line2 ( 4 0h~ 4 fh) dd ram line 5 ( 7 0h~ 7 fh) lcd ls2, ls1 = 00 dd ram line 3 ( 50h~5fh) dd ram line 4 ( 60h~6fh) dd ram line 2 ( 4 0h~ 4 fh) dd ram line 3 ( 5 0h~ 5 fh) lcd dd ram line 4 ( 6 0h~ 6 fh) dd ram line 5 ( 7 0h~ 7 fh) dd ram line 3 ( 5 0h~ 5 fh) dd ram line 4 ( 6 0h~ 6 fh) lcd dd ram line 5 ( 7 0h~ 7 fh) dd ram line 1 ( 3 0h~ 3 fh) dd ram line 4 ( 6 0h~ 6 fh) dd ram line 5 ( 7 0h~ 7 fh) lcd dd ram line 1 ( 3 0h~ 3 fh) dd ram line 2 ( 4 0h~ 4 fh) dd ram line 1 ( 3 0h~ 3 fh) figure 1 1 . line shift mode display at 4 -line lcd
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 27 line blink display control re rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 0 1 0 lb4 lb3 lb2 lb1 displays the specified line in black-and-white form. the specified line corresponds to the address line of ddram. display the specified line of the ddram in black-and-white form by setting lb4 to lb1. blinking is performed at the same frequency as cursor blink. if blinking is caused to occur at the same time, the cursor position will be hard to know. lb 4 = 0: d isplays the data for line 4 of the ddram in standard form (no blink) (ddram 60h to 6fh) = 1: d isplays the data for line 4 of the ddram in black-and-white reverse blink form (ddram 60h to 6fh) lb 3 = 0: d isplays the data for line 3 of the ddram in standard form (no blink) (ddram 50h to 5fh) = 1: d isplays the data for line 3 of the ddram in black-and-white reverse blink form (ddram 50h to 5fh) lb2 = 0: d isplays the data for line 2 of the ddram in standard form (no blink) (ddram 40h to 4fh) = 1: d isplays the data for line 2 of the ddram in black-and-white reverse blink form (ddram 40h to 4fh) lb1 = 0: di splays the data for line 1 of the ddram in standard form (no blink) (ddram 30h to 3fh) = 1 : d isplays the data for line 1 of the ddram in black-and-white reverse blink form (ddram 30h to 3fh) double height mode re rs db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 0 1 0 dh4 dh3 dh2 dh1 double height m ode instruction field selects double height line type. dh4 = 0: d isplays the data for line 4 of the ddram in standard form (ddram 60h to 6fh) = 1: d isplays the data for line 4 of the ddram in vertical double size form (ddram 60h to 6fh) dh 3 = 0: d isplays the data for line 3 of the ddram in standard form (ddram 50h to 5fh) = 1: d isplays the data for line 3 of the ddram in vertical double size form (ddram 50h to 5fh) dh2 = 0: d isplays the data for line 2 of the ddram in standard form (ddram 40h to 4fh) = 1: d isplays the data for line 2 of the ddram in vertical double size form (ddram 40h to 4fh) dh1 = 0: d isplays the data for line 1 of the ddram in standard form (ddram 30h to 3fh) = 1: d isplays the data for line 1 of the ddram in vertical double size form (ddram 30h to 3fh)
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 28 3 0 h -------------------- 3 f h 4 0 h -------------------- 4 f h 5 0 h -------------------- 5 f h 6 0 h -------------------- 6 f h 7 0 h -------------------- 7 f h 3 0 h -------------------- 3 f h 4 0 h --------------- 4f h 5 0 h -------------------- 5 f h 6 0 h --------------- 6f h 7 0 h -------------------- 7 f h 3 0 h -------------------- 3 f h 4 0 h --------------- 4f h 5 0 h -------------------- 5 f h 6 0 h --------------- 6f h 7 0 h -------------------- 7 f h 3 0 h -------------------- 3 f h 4 0 h --------------- 4f h 5 0 h -------------------- 5 f h 6 0 h --------------- 6f h 3 0 h -------------------- 3 f h 4 0 h --------------- 4f h 5 0 h -------------------- 5 f h 6 0 h --------------- 6f h 7 0 h -------------------- 7 f h ddram area display area 7 0 h -------------------- 7 f h xxh : ddram address (1) i nitial s tatus (2) dd4, dd3, dd2, dd1= 1010 (3) 1 - line s hift (4) 2 - line s hift (5) 3 - line s hift figure 1 2. line double height mode display
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 29 display control re rs db7 db6 db5 db4 db3 db2 db1 db0 0/1 0 0 0 1 0 c b re d display control instruction field controls cursor / blink / display on / off. c: cursor on / off control bit when c = "high", cursor is turned on when c = "low", cursor is disappeared in current display (default). b: cursor blink on / off control bit when c = "high" and b = "high", ks00 94 make lcd alternate between inverting display character and normal display character at the cursor position with about a half second. on the contrary, if c = "low", only a normal character is displayed regardless of "b" flag. when b = "low", blink is off (default). re: extended register access is specified by setting re when re = ? high ? , e xtended register on when re = ? low ? , e xtended register off d: display on / off control bit when d = "high", entire display is turned on. when d = "low", display is turned off, but display data are remained in ddram (default). table 1 1 . cursor attributes c, b display state 1, 0 1, 1 (blinking mode) 0, 0 0, 1
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 30 power save re rs db7 db6 db5 db4 db3 db2 db1 db0 0/1 0 0 1 0 0 * * os ps *: d on ? t care power save instruction field is used to control the oscillator and to set or to reset the power save mode. os: o scillator on / off control bit when os = "high", internal oscillator is turned on when os = "low", internal oscillator is turned off (default) ps: p ower save on / off control bit when ps = "high", power save mode is turned on when ps = "low", power save mode is turned off (default) power control (1) re rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 0 1 hpm v r v f vc power control instruction field sets h igh power mode and voltage regulator / converter / follower on / off. hpm: high power mode control bit when hpm = ? high ? , h igh power mode is turned on when hpm = ? low ? , h igh power mode is turned off ( default) vr: v oltage regulator circuit control bit when vr = "high", voltage regulator is turned on when vr = "low", voltage regulator is turned off (default) vf: v oltage follower circuit control bit when vf = "high", voltage follower is turned on when vf = "low", voltage follower is turned off (default) vc: v oltage converter circuit control bit when vc = "high", voltage converter is turned on when vc = "low", voltage converter is turned off (default) note: the oscillation circuit must be turned on for the voltage converter circuit to be active. power control (2) re rs db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 0 1 irs bs ir1 ir0 irs: initial resistors select when irs = ? high ? , i nternal resistors are used for regulator when irs = ? low ? , external resistors are used for regulator (default) bs: bias select when bs = ? high ? , it ? s 1/4 bias when bs = ? low ? , it ? s 1/5 bias (default) ir1, ir0: internal resistor ratio select when ir1,ir0 = 00, (1 + rb/ ra) = 2.81, v0 = 5.60v when ir1,ir0 = 01, (1 + rb/ ra) = 3.27, v0 = 6.54v when ir1,ir0 = 10, (1 + rb/ ra) = 3.50, v0 = 7.00v when ir1,ir0 = 11, (1 + rb/ ra) = 3.00, v0 = 6.00v
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 31 system set (1) re rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 0 1 1 0 r1 r0 cs cg r1, r0: selects an option rom when r1, r0 = 00, s tandard rom (160 characters) + option rom1 (96 characters) when r1, r0 = 01, s tandard rom (160 characters) + option rom2 (96 characters) when r1, r0 = 10, s tandard rom (160 characters) + option rom3 (96 characters) when r1, r0 = 11, s tandard rom (160 characters) + option rom4 (96 characters) cs : d ata shift direction of common c s sets the shift direction of common display data when c s = "high", com right shift when c s = "low", com left shift (default) ( r efer to table 9 and figure 13 ) cg: cgram enable bit when cg = "high", cgram can be u sed and you can use this ram for eight special character area. (00h - 0 5 h= cgram font display) when cg = "low", cgram is disabled. cgrom (00h - 0 5 h) can be u sed and the additional current consumption is saved by using this mode (default) (00h - 0 5 h= cgrom font display) system set (2) re rs db7 db6 db5 db4 db3 db2 db1 db0 1 0 0 1 1 0 * * ss * *: d on ? t care ss: the normal / r everse character display of seg is specified by setting ss. when ss = ? low ? , n ormal display of seg when ss = ? high ? , r everse display of seg rom f ont (ss, cs) = (0, 0 ) (ss, cs) = (1, 0) (ss, cs) = (0, 1) (ss, cs) = (1, 1) figure 13. example of display a ccording to ss and cs - bit
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 32 ddram address set re rs db7 db6 db5 db4 db3 db2 db1 db0 0 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 above r am address set instruction field sets ddram and electronic volume register in the address counter . before writing / reading data into / from the dd ram, set the address by dd ram address s et instruction. next, when data are written / read in succession, the address is automatically increased by 1. after accessing 7fh, the address of ac is 00h. the read data from the unused address are unknown. the address ranges are 00h - 7fh. table 12. ram address mapping (re = 0) address 0 1 2 3 4 5 6 7 8 9 a b c d e f 00h unused ev test unused 1 0h unused 20h unused 30h ddram line - 1 40h ddram line - 2 50h ddram line - 3 60h ddram line - 4 70h ddram line - 5 ev: electric volume ram test: testing register, d on ? use it.
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 33 cgram address set re rs db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 ac6 ac5 ac4 ac3 ac2 ac1 ac0 above r am address s et instruction field sets cg ram , segment icon ram in the address counter . before writing / reading data into / from the cg ram / iconram , set the address by cg ram address set instruction. next, when data are written/read in succession, the address is automatically increased by 1. after accessing 7fh, the address of ac is 00h. the read data from the unused address are unknown. the address ranges are 00h - 7fh. table 1 3 . ram address mapping (re = 1) address 0 1 2 3 4 5 6 7 8 9 a b c d e f 00h cgram (00h) cgram (01h) 10h cgram (02h) cgram (03h) 20h cgram (04h) cgram (05h) 30h unused 40h unused 50h unused 60h iconram (s1 - s80) 70h iconram (s81 - s160)
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 34 write data re rs db7 db6 db5 db4 db3 db2 db1 db0 0/1 1 d7 d6 d5 d4 d3 d2 d1 d0 this instruction field make ks009 4 write binary 8-bit data to ddram / cgram / iconram or register. the ram address to be written into is determined by previous dd/cgram address set instruction. after writing operation, the address counter (ac) automatically increased by 1. read data re rs db7 db6 db5 db4 db3 db2 db1 db0 0/1 1 d7 d6 d5 d4 d3 d2 d1 d0 ddram / cgram / iconram data read instruction. each ram is selected by address set instruction. and then you can read the ram data. you can get correct ram data from second read transaction. the first read data after setting ram address is dummy data, so the correct ram data come from the second read transaction. after reading operation, the address counter (ac) is increased by 1 automatically. nop re rs db7 db6 db5 db4 db3 db2 db1 db0 0/1 0 0 0 0 0 0 0 0 0 no operation command it is recommended to add this command at each breakpoint of the program. t est m ode re rs db7 db6 db5 db4 db3 db2 db1 db0 0/1 0 0 0 0 0 * * * * *: d on ? t care an ic test mode set command. don ? t use it any case.
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 35 initializing & power save mode setup hardware reset when resetb pin = "low", ks009 4 can be initialized as the following state. (1) control display on / off instruction c = 0: cursor off b = 0: blink off re = 0: extension register off d = 0: display off (2) power save set instruction os = 0: oscillator off ps = 0: power save off (3) power control set instruction hpm = 0: h igh power mode off vr = 0: voltage regulator off vf = 0: voltage follower off vc = 0: voltage converter off irs = 1: f or built-in resistor bs = 0: 1/5 bias ir1, 0 = 00: rb / ra = 2.81 (4) system set instruction r1, r0 = 00: main rom + option rom c s = 0: com left shift ss = 0 : n ormal display character cg = 0: cgram is not used (5) return home address counter = 3 0h (6) electronic contrast control register: a ddress 10h = data (0, 0, 0, 0, 0) (7) in case of 4-bit interface mode selection ks009 4 considers the first 4-bit data from mpu as the high order bits. n ote : if initialization is not done by the resetb pin at application, unknown condition might result. then you can initialize by instruction.
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 36 resetb pulse width t rw 10 m s resetb start time t resetb 50ns v dd resetb t resetb t rw figure 1 4 . reset timing
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 37 initializing and power save setup initializing by instruction v dd -v ss power on keep resetb pin = "l" when the power is stable, release the reset state (resetb = " h " ). waiting for 10us or more command input 1. function set (n, s, cg) 2. electronic volume register setup (0 8 h) 3. power save (ps: power save off, os: osc on) 4. power control (v r , v f , v c are all on) waiting for 50 0 u s or more command input 7. display control (d: on) end of initialization command input 5. ram address set command input 6. data writing (ram clear) (ddram = 20h, cgram = 00h) note: at command 5 and 6, the internal ram should be cleared. to clear ddram, re bit should be set 0, set address at 3 0h (first ddram) and then write 20h (space character code) 80 times to clear cgram (re=1) , re bit should be set 1, set address at 0 0h (first cgram) and then write 00h (null data) 48 times to clear iconram (re=1) , re bit should be set 1, set iconram address at 6 0h (first iconram) and then write 00h (null data) 32 times
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 38 sleep mode set or release by instruction a) sleep mode set b) sleep mode release end of initialization normal operation status (power save is off and oscillator is on.) command input 1. display control (d: off) 2. power save (ps: power save on, os: osc off) 3. power control (v r , v f , v c are all off) enter the sleep mode sleep mode command input 3. display control (d: on) command input 1. power save (ps: power save off, os: osc on) 2. power control (v r , v f , v c are all on) return to normal operation waiting for 50 0 us or more
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 39 recommendation of power on / off sequence a) power on sequence b) power off sequence power on voltage converter on [v r , v f , v c = 0, 0, 1 ] voltage regulator on [v r , v f , v c = 1, 0 , 1 ] operation command input waiting for 3 1ms voltage follower on [v r , v f , v c = 1, 1, 1] waiting for 3 1ms operation command input voltage regulator off [v r , v f , v c = 0 , 1 , 1] voltage follower off [v r , v f , v c = 0 , 0, 1 ] operation command input waiting for 3 50ms voltage converter off [v r , v f , v c = 0, 0, 0] waiting for 3 1ms display off waiting for 3 1ms
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 40 lcd driving power supply circuit the power supply circuit produces lcd panel driving voltage at low power consumption. the lcd d riving power supply circuit consists of voltage converter, voltage regulator, and voltage follower. it is controlled by power control instruction. table 14 shows how the lcd driving power supply circuit works by power control instruction sets. table 1 4 . power supply control mode set vr vf vc voltage regulator voltage follower voltage converter vout pin vr pin v0, v1, v2, v3, v4 pin 1 1 1 enable enable enable internal voltage output used for voltage adjustment internal voltage output 1 1 0 enable enable disable external voltage input used for voltage adjustment internal voltage output 0 1 0 disable enable disable open open v1 ~ v4: internal voltage output v0: e xternal voltage input 0 0 0 disable disable disable open open v0 ~ v4: e xternal voltage input n ote : sec recommendation is to use only the case listed above table. voltage converter the voltage converter circuit generates positive 4 times voltage of 2.0 v that is generated internally. vout is generated from the voltage converter. and this conversion voltage is used in the built-in voltage regulator circuit. this application circuit is same as 3 times dc/dc converter. v ss 2.0 v (internal) vout 4 x 2 . 0 v = 8 . 0 v vdd cap1+ cap1- cap2+ cap2- vout ks009 4 v dd + - + - - + figure 1 5 . dc/dc converter output and circuit
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 41 voltage regulator the voltage regulator circuit is used to obtain an appropriate lcd panel driving voltage. this voltage is obtained by adjusting resistors ra and rb as shown in equation (1), and by setting electronic contrast control data bits, see equation (2). the potential of v0 pin can be adjusted within vout - v ref . v ref is the internal constant voltage source of the chip and this value is 2.0v in the condition v dd 3 2. 2 v n voltage regulation by adjusting resistors ra, rb when ref is "low" rb v0 = ( 1 + ) x v ref --- (1) ra the internal v ref of voltage regulator has the temperature compensation function, and the temperature coefficient is approximately 0% _ + inside chip gnd ra rb v ss vout v0 vr v ref figure 1 6 . voltage regulator circuit
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 42 electronic contrast control (32 steps) electronic contrast control data bits is 10h = (d4, d3, d2, d1, d0). voltage regulation is adjusted as 32-contrast step according to the value of electronic contrast control data bits. lcd drive voltage v0 has one of 32 voltage values if 5-bit data is set to the electronic contrast control register ( re = 0 address 0 8 h). when using the electronic contrast control function, you need to turn the voltage regulators on using power control instruction. when ref = "low" rb v0 = ( 1 + ) x v ev --- (2) ra v ev = v ref - n a (n = 0, 1, 2, ... 30, 31) a = v ref / 150 table 1 5 . electronic contrast control register no. d7 d6 d5 d4 d3 d2 d1 d0 n a a v0 contrast 1 - - - 0 0 0 0 0 0 a (default) 2 - - - 0 0 0 0 1 1 a 3 - - - 0 0 0 1 0 2 a 4 - - - 0 0 0 1 1 3 a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 - - - 1 1 1 1 0 30 a 32 - - - 1 1 1 1 1 31 a maximum . . . . . . . minimum high . . . . . . . low note: 1. "-" : don?t care
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 43 _ + inside chip gnd ra rb v ss vout v0 vr v ref + v ev - figure 17 . electronic contrast control circuit the voltage rage of the v5 output can be adjusted by changing the built-in resister ratio (1 + rb / ra) by command. reference values are shown in table 16. table 16. v0 v oltage r egulating b uilt-in r esister r atio se t v alues ( r eference v alues) command ir1 ir0 (1+rb / ra) v0 0 0 1 1 0 1 0 1 2.81 3.27 3.50 3.00 5.60v 6.54v 7.00v 6.00v
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 44 voltage generator circuit cap1+ cap1- vdd cap2+ c1: 1 ~ 4.7uf c2: 0.1uf vss v4 v3 v2 c1 c1 c1 c2 c2 c2 c2 c2 - + - + gnd gnd v0 v1 rb ra vr vout cap2- vdd figure 18 . when built-in power supply is used (v r , v f , v c = 1, 1, 1) cap1+ cap1- vdd cap2+ vss v4 v3 v2 c2 c2 c2 c2 c2 - + gnd gnd v0 v1 rb ra vr vout cap2- cap1+ cap1- vdd cap2+ vss v4 v3 v2 - + gnd v0 v1 vr vout cap2- vdd vss v4 v3 v2 gnd v0 v1 vr gnd cap1+ cap1- cap2+ vout cap2- (v r , v f , v c = 1 , 1, 0 ) (v r , v f , v c = 0, 1 , 0 ) (v r , v f , v c = 0, 0, 0) all capacitor is c2. c2: 0.1 to 4.7uf external power supply external power supply external power supply vdd vdd vdd figure 19 . when external power supply is used
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 45 mpu interface mpu vcc gnd a0 a1-a7 iorq rd wr d0-d7 res decoder rs csb e_rd rw_wr db [0:7] resetb ks009 4 ps mi if resetb vdd vss vdd vdd vdd figure 2 0 . parallel interfacing with 8080-series microprocessors mpu vcc gnd a0 a1-a7 vma r/w e d0-d7 res decoder rs csb rw_wr e_rd db [0:7] resetb KS0094 ps mi if resetb vdd vss vdd vdd vdd figure 2 1 . parallel interfacing with 6800-series microprocessors
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 46 mpu vcc gnd port4 port3 port1 port2 res rs csb scl(db6) si(db7) resetb ks009 4 mi if e_rd rw_wr ps resetb vdd vss vdd or vss vdd figure 2 2 . clock synchronized serial interfacing with any microprocessors
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 47 application information for lcd panel chip bottom & lower view ( c s bit = "0", dirs = "0") seg80 seg79 seg78 seg77 seg76 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 ................................................ com i1 com 16 com 15 com 14 com 13 com 12 com 11 com 10 com 9 com 8 com 7 com 6 com 5 com 4 com 3 com 2 com1 comi 1 bottom view com i2 com 32 com 31 com 30 com 29 com 28 com 27 com 26 com 25 com 24 com 23 com 22 com 21 com 20 com 19 com 18 com1 7 comi 2 figure 2 3 . chip bottom & lower view (c s bit = "0", dirs = "0")
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 48 chip bottom & upper view ( c s bit = "1", dirs = "1") seg1 seg2 seg3 seg4 seg5 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 ................................................ com i2 com 17 com 18 com 19 com 20 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 com 30 com 31 com32 comi 2 bottom view com i1 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com1 6 comi 1 figure 2 4 . chip bottom & upper view (c s bit = "1", dirs = "1")
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 49 chip top & lower view ( c s bit = "0", dirs = "1") seg1 seg2 seg3 seg4 seg5 seg71 seg72 seg73 seg74 seg75 seg76 seg77 seg78 seg79 seg80 ................................................ com i2 com 32 com 31 com 30 com 29 com 28 com 27 com 26 com 25 com 24 com 23 com 22 com 21 com 20 com 19 com 18 com1 7 comi 2 top view com i1 com 16 com 15 com 14 com 13 com 12 com 11 com 10 com 9 com 8 com 7 com 6 com 5 com 4 com 3 com 2 com1 comi 1 figure 2 5 . chip top & lower view (c s bit = "0", dirs = "1")
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 50 chip top & upper view ( c s bit = "1", dirs = "0") seg80 seg79 seg77 seg76 seg75 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 ................................................ com i1 com 1 com 2 com 3 com 4 com 5 com 6 com 7 com 8 com 9 com 10 com 11 com 12 com 13 com 14 com 15 com16 comi 1 top view com i2 com 17 com 18 co m 19 com 20 com 21 com 22 com 23 com 24 com 25 com 26 com 27 com 28 com 29 com 30 com 31 com32 comi 2 figure 2 6 . chip top & upper view (c s bit = "0", dirs = "1")
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 51 frame frequency 1/18 duty (2-line m ode) v0 v1 v4 vss com1 1-line selection period 1 2 17 18 . . . . . . . . . . . . . 1 2 17 18 1 2 . . . . . . . . . . . . . . . . . . . . . . . 1 frame 1 frame 1-line selection period = 16 clocks one frame = 16 x 1 8 x 44 . 44 us = 1 2 . 8 ms (1 clock = 44 . 44 us at f osc = 45 khz) frame frequency = 1 / 1 2 . 8 ms = 78.1 hz 1/2 6 duty (3-line m ode) v0 v1 v4 vss com1 1-line selection period 1 2 2 5 2 6 . . . . . . . . . . . . . 1 2 2 5 2 6 1 2 . . . . . . . . . . . . . . . . . . . . . . . 1 frame 1 frame 1-line selection period = 16 clocks one frame = 16 x 2 6 x 29.63 us = 1 2 . 33 ms (1 clock = 2 9.63 us at f osc = 4 5 khz) frame frequency = 1 / 1 2 . 33 ms = 81.1 hz 1/ 34 duty (4-line m ode) v0 v1 v4 vss com1 1-line selection period 1 2 33 34 . . . . . . . . . . . . . 1 2 33 34 1 2 . . . . . . . . . . . . . . . . . . . . . . . 1 frame 1 frame 1-line selection period = 16 clocks one frame = 16 x 34 x 22.2 us = 1 1.97 ms (1 clock = 2 2.2 us at f osc = 4 5 khz) frame frequency = 1 / 11.97 ms = 83 hz
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 52 maximum absolute rat ings table 17. maximum absolute ratings characteristic symbol value unit power supply voltage (1) v dd -0.3 to + 7.0 v power supply voltage (2) vout, v0 -0.3 to + 9 .0 v power supply voltage (3) v1, v2, v3, v4 -0.3 to v0 v input voltage v in -0.3 to v dd +0.3 v operating temperature t opr -30 to +85 o c storage temperature t stg -55 to +125 o c n ote 1: all the voltage levels are based on v ss = 0v. n ote 2: voltage greater than above may damage the circuit voltage level : vout 3 v0 3 v dd 3 v ss voltage level : v0 3 v1 3 v2 3 v3 3 v4 3 v ss
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 53 electrical characteristics dc characteristics table 18. dc characteristics (v dd = 2. 2 v to 3.6v, ta = -30 to +85 o c) item symbol condition min. typ. max. unit operating voltage v dd - 2.2 - 3.6 v i dd1 display operation v lcd =6v without load no access from mpu - - 95 i dd2 access operation from mpu ( fcyc = 200k hz) - - 500 supply current (v dd = 3v, ta = 25 o c) i dds1 sleep operation without load oscillator off, power save on - - 5 ua v ih - 0. 8 v dd v dd input voltage v il - vss 0. 2 v dd v v oh i oh = -1ma, v dd =2.4v v dd - 0.4 output voltage v ol i ol = 1ma, v dd =2.4v 0.4 v input leakage current i iz v in = 0v to v dd -1 - 1 ua output leakage current i oz v in = 0v to v dd -3 3 ua r com io = 50ua - - 5 r on resistance r seg io = 50ua - - 10 k w frame frequency (internal osc) f fr v dd = 3v, ta = 25 o c (4-line mode) 70 85 100 hz conversion efficiency v ef rl = 95 99 - % voltage converter output voltage v out ta = 25 o c, c = 1uf 7 . 5 8 . 0 8 .5 v voltage regulator reference voltage v ref ta = 25 o c 1.94 2.0 2.06 lcd driving voltage v lcd v lcd = v0 - vss 3 .0 - 7 .0 v
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 54 ac characteristics parallel write interface (68 mode) (v dd = 2. 2 v to 3.6v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit e_rd cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 e_rd pulse width high t wh 450 - - e_rd pulse width low t wl 150 - - rs and csb setup time t su1 60 - - rs and csb hold time t h1 30 - - db setup time t su2 100 - - db hold time t h2 50 - - ns rs,csb rw_wr e_rd db0~db7 t su1 t h1 t wh t wl t r t su2 t c t h2 t f valid data figure 27. write timing diagram (68-series)
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 55 parallel read interface (68 mode) (v dd = 2. 2 v to 3.6v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit e_rd cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 e_rd pulse width high t wh 450 - - e_rd pulse width low t wl 150 - - rs and csb setup time t su 60 - - rs and csb hold time t h 30 - - db output delay time t d 100 - - db output hold time t dh 50 - - ns rs ,csb rw_wr e_rd db0~db7 t su t h t wh t wl t r t c t d t dh valid data t f figure 28. read timing diagram (68-series)
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 56 parallel write interface (80 mode) (v dd = 2. 2 v to 3.6v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit rw_wr cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 rw_wr pulse width high t wh 150 - - rw_wr pulse width low t wl 450 - - rs and csb setup time t su1 60 - - rs and csb hold time t h1 30 - - db setup time t su2 100 - - db hold time t h2 50 - - ns rs ,csb rw_wr e_rd db0~db7 t su1 t h1 t wl t wh t f t su2 t c t h2 t r valid data figure 29. write timing diagram (80-series)
34 com / 80 seg driver & controller for stn lcd preliminary spec. ver. 0. 4 ks009 4 57 parallel read interface (80 mode) (v dd = 2. 2 v to 3.6v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit e_rd cycle time t c 650 - - pulse rise / fall time t r ,t f - - 25 e_rd pulse width high t wh 150 - - e_rd pulse width low t wl 450 - - rs and csb setup time t su 60 - - rs and csb hold time t h 30 - - db output delay time t d 100 - - db output hold time t dh 50 - - ns rs ,csb rw_wr e_rd db0~db7 t su t h t wl t wh t f t c t d t dh valid data t r figure 30. read timing diagram (80-series)
KS0094 preliminary spec. ver. 0. 4 34 com / 80 seg dr iver & controller for stn lcd 58 clock synchronized serial mode (v dd = 2. 2 v to 3.6v, ta = -30 to +85 o c) characteristic symbol min. typ. max. unit scl clock cycle time t c 1000 - - pulse rise / fall time t r ,t f - - 25 scl clock width (high, low) t w 300 - - csb setup time t su1 150 - - csb hold time t h1 700 - - rs data setup time t su2 50 - - rs data hold time t h2 300 - - si data setup time t su3 50 - - si data hold time t h3 50 ns csb scl rs si tsu3 t su2 tsu1 th3 t h2 t h1 t c t r t w t w t f figure 31. clock synchronized serial interface mode timing diagram

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